1. Field of the Invention
The present invention is directed generally to solid state memory circuits and, more particularly, to the input/output devices used in such circuits.
2. Description of the Background
Solid state memory circuits are comprised of a plurality of memory cells arranged in an array. The memory cells of one row are connected to a common digitline while each cell in the row is connected to a unique wordline. Conversely, the memory cells of one column are connected to a common wordline while each cell in the column is connected to a unique digitline. To address a cell for either a read or a write operation requires that both a digitline and a wordline be activated, with the cell at the intersection of that digitline and wordline being accessed.
To write information into the array or read information out of the array a number of peripheral devices must be used. Those devices generally include isolation transistors, equilibration and bias circuits, N-sense amplifiers, P-sense amplifiers, and switches for connecting selected digitlines of the array to input/output signal lines. Each of the aforementioned devices performs a specific function which is well known in the art. It is also well known that the aforementioned devices must be operated according to a precise timing sequence to ensure that the desired operation, a read or write operation, is properly performed.
The isolation transistors are placed between the digitlines of the memory array and the sense amplifier components. The isolation transistors can, if properly positioned, electrically isolate a portion of the array to thereby lessen the capacitance of the digitline being driven by the sense amplifiers. Reducing the capacitance speeds read-write times, reduces power consumption, and extends refresh for the isolated array. The isolation transistors also provide resistance between the sense amplifier and the digitlines. That resistance stabilizes the sense amplifiers and speeds up the sensing operation.
The equilibration and bias circuits ensure that digitlines, which form a column pair, are at the same voltage before the wordline is fired. Any offset voltage appearing between the pair directly reduces the effective signal produced during the access operation. The bias circuit operates in conjunction with the equilibration circuit to ensure that the digitline pair remains at the prescribed voltage for sensing. Normally, digitlines that are at Vcc and ground equilibrate to Vcc/2 volts. Bias circuits ensure that this occurs and also guarantee that the digitlines remain at Vcc/2, despite leakage paths that would otherwise discharge them.
The N-sense amplifiers and P-sense amplifiers work together to detect the access signal voltage and to help drive the digitlines to Vcc and ground.
As might be expected, the layout and fabrication of the isolation transistors, circuitry for digitline equilibration and bias, N and P sense amplifiers, and digitline to I/O signal line switches is a complicated process. All of the circuits that interface physically with the memory array are called pitch cells. The designation of pitch cell comes from the requirement that the physical layout of the pitch cell circuits be constrained by the digitline and wordline pitches of an array of m-bits. For example, the sense amplifiers for a specific digitline pair column are generally laid out within the space of four digitlines. The ratio of one sense amplifier for every four digitlines is commonly referred to as quarter pitch or four pitch. Because of the space requirements imposed on this collection of components, the design engineer is faced with the challenge of providing physically small components which fit within the allotted space which at the same time operate properly within the parameters established for such circuitry. Thus, the need exists for improvements in such access circuitry.